A divider realized in hardware is used as a basic part of a semiconductor integrated circuit. In recent years, the chip size of the semiconductor integrated circuit is increasing through extension of a function of the semiconductor integrated circuit, while the chip size of the semiconductor integrated circuit is required to be reduced for saving a manufacturing cost of the semiconductor integrated circuit.
In the development of a large-scale SOC (System On a Chip), the need of a divider circuit is increasing in which the circuit scale is suppressed even if a bit width of a register set with a dividend or a divisor increases.
A technique of a recovery-type divider circuit is disclosed in Patent Literature 1 (JP 07-160479A) in which a power consumption amount can be reduced.
First, a general recovery-type divider circuit will be described.
FIG. 1 is a block diagram showing the whole configuration of a recovery-type divider circuit. The recovery-type divider circuit of FIG. 1 is provided with a register X of 16 bits, a register Q of 16 bits and partial dividers D0 to D15. Also, although being not shown in FIG. 1, a 16-bit register Y is provided to store divisor data. The register X stores dividend data. Quotient data when the dividend data stored in the register X is divided by the divisor stored in the register Y can be obtained by sequentially operating the partial dividers D15 to D0. The operation results by the partial dividers D15 to D0 are finally stored in the register Q from MSB (Most Significant Bit) to LSB (Least Significant Bit) as the quotient data. Remainder data can be determined from the output R0 of the last-stage partial divider D0.
FIG. 2 is a block diagram showing the configuration of the partial divider D15 shown in FIG. 1. The partial divider D15 is provided with a subtractor J15 and a partial remainder selecting circuit S15. The subtractor J15 subtracts the divisor data stored in the register Y from bit data X15 as the MSB of the register X and outputs the subtraction result data A15 to the partial remainder selecting circuit S15. Also, the subtractor J15 outputs bit data B15 to the Q15 as the MSB of the register Q and the input S of the partial remainder selecting circuit S15. The bit data B15 is “0” if the subtraction result data A15 is negative and “1” if the subtraction result data A15 is equal to or more than “0”. The partial remainder selecting circuit S15 is a selector (a multiplexer) which outputs either of data at an input 0 or data at an input 1 as the output U according to the input S. If the value of the input S is “1”, the partial remainder selecting circuit S15 outputs the subtraction result data A15 at the input 1 as the partial remainder data R15. If the value of the input S is “0”, it outputs the MSB X15 of the register X at the input 0 as the partial remainder data R15.
FIG. 3 is a block diagram showing the configuration of the partial divider used for the partial dividers D14 to D0 of FIG. 1. The partial divider Dn is provided with a register Tn, a subtractor Jn and a partial remainder selecting circuit Sn. The register Tn synthesizes data Wn by adding data Xn to the LSB side of data R(n+1) from the partial divider D(n+1). For example, Wn=0101101 if R(n+1) is 010110 and Xn is “1”. The partial dividers D14 to D0 are different from the partial divider D15 of FIG. 2 in that the register Tn which stores the data Wn is further provided and that the subtractor Jn calculates a difference Wn-Y by using Wn not X15.
The subtractor Jn subtracts the divisor data stored in the register Y from the data Wn stored in the register Tn and outputs the subtraction result data An to the partial remainder selecting circuit Sn. Also, the subtractor Jn outputs bit data Bn to Qn of the register Q and the input S of the partial remainder selecting circuit Sn. The bit data Bn is “0” if the subtraction result data An is negative, and “1” if the subtraction result data is equal to or more than “0”. The partial remainder selecting circuit Sn is a selector (a multiplexer) which outputs either of input 0 or input 1 as an output S according to the input S. The partial remainder selecting circuit Sn outputs the subtraction result data An of the input 1 as the partial remainder data Rn if the value of the input S is “1”, and outputs Wn of the input 0 as the partial remainder data Rn if the value of the input S is “0”.
By adopting the above configuration, the quotient when the dividend stored in the register X is divided by the divisor stored in the register Y is stored in the register Q. A remainder when the dividend stored in the register X is divided by the divisor stored in the register Y is outputted as R0 by the output U of the partial remainder selecting circuit Sn of the partial divider circuit D0.
The general recovery-type divider circuit is as described above.
The technique of a new divider circuit is disclosed in JP H07-160479A (Patent Literature 1), in which the above-described recovery-type divider circuit is improved to reduce a consumed power amount. In this technique, the improvement to reduce the consumed power amount is applied to the above-described partial dividers D15 to D0. FIG. 4 is a block diagram showing the configuration of the partial divider used for the partial divider D15 in Patent Literature 1. FIG. 5 is a block diagram showing the configuration of the partial divider circuit used for the partial dividers D14 to D0 in Patent Literature 1. The improved recovery-type divider circuit is different from the general recovery-type divider circuit in that an operation result predicting circuit Fn is provided in FIG. 4 and FIG. 5. When the operation result predicting circuit Fn can predicts the above-described data En without carrying out an operation of the subtractor Jn, the operation result predicting circuit Fn determines a selection control signal En without waiting for the completion of the subtractor Jn, and outputs it to the input S of the partial remainder selecting circuit Sn. Thus, the partial remainder selecting circuit Sn can select Rn earlier, so that it determines the logic state of the partial remainder selecting circuit Sn at an earlier stage to allow the consumed power amount due to change of the logic state to be reduced.
Here, the circuit scale of the divider circuit in the Patent Literature 1 is estimated roughly when the bit width of the register which stores the dividend data is 16 bits. First, the register X of 16 bits is configured of 128 elements, supposing that a portion of the register for 1 bit is configured of 8 elements. In the same way, the register Q is configured of 128 elements. Regarding to the partial divider Dn, the circuit scale of the partial divider D14 is estimated in which the circuit scale of the Tn register is the smallest. Because the partial divider D14 contains the register Tn, the subtractor Jn, the operation result predicting circuit Fn and the selector Sn, it is estimated that the circuit scale of the partial divider circuit D14 is about 72 elements. This is, it is configured of 72 elements of 16 elements for 2-bit register Tn, 38 elements for the subtractor Jn (a NOT circuit and a full adder), 14 elements for the predicting circuit Fn (three NOT circuits, one 2-input NAND circuit, and 2-input inverted OR circuit), and 4 elements for the selector Sn (a 2-to-1 selector). Therefore, the circuit scale of the divider circuit in Patent Literature 1 is the register X+the register Q+partial divider circuit Dn×16=128+128+1152=1408 (elements).
In the above-mentioned recovery-type divider circuit, when the bit width of the register increases, the circuit scale increases according to a power of an increase rate of the bit width. The reason is in that in the whole configuration of the recovery-type divider circuit shown in FIG. 1, the circuit scale increases with increase of the bit width in each partial divider as well as the number of partial dividers increases with increase of the bit width.
That is, supposing that the circuit scale of the above-mentioned n-bit recovery-type divider circuit is S1, the following equation (1) is met:S1=(circuit scale of each partial divider in n-bit divider circuit)×n  (1)
Supposing that the circuit scale of the m-bit recovery-type divider circuit in which the bit width of the register has increased is S2, the following equation (2) is met:S2=(circuit scale of each partial divider in m-bit divider circuit)×m =((circuit scale of each partial divider in n-bit divider circuit)×(m/n))×(n×(m/n))=S1×(m/n)2  (2)
For example, when n=16 (bits), m=32 (bits), the increasing rate of the circuit scale is S2=1152×(32/16)2=4608 (elements). In this way, the circuit scale of the conventional recovery-type divider circuit increases greatly as the bit width of the register increases.